1. Field of the Invention
The invention relates generally to communication protocols and interfaces, and more specifically, to a system and method for communicating with an integrated circuit.
2. Related Art
System-on-chip devices (SOCs) are well-known. These devices generally include a processor, one or more modules, bus interfaces, memory devices, and one or more system busses for communicating information. Because multiple modules and their communications occur internally to the chip, access to this information is generally difficult when problems occur in software or hardware. Thus, debugging on these systems is not straightforward. As a result of development of these SOCs, specialized debugging systems have been developed to monitor performance and trace information on the chip. Such systems typically include dedicated hardware or software such as a debug tool and debug software which accesses a processor through serial communications.
However, debugging an SOC generally involves intrusively monitoring one or more processor registers or memory locations. Accesses to memory locations are sometimes destructive, and a data access to a location being read from a debugging tool may impede processor performance. Similarly, accesses are generally performed over a system bus to the processor, memory, or other module, and may reduce available bandwidth over the system bus for performing general operations. Some debugging systems do not perform at the same clock speed as that of the processor, and it may be necessary to slow the performance of the processor to enable use of debugging features such as obtaining trace information. By slowing or pausing the processor, some types of error may not be reproduced, and thus cannot be detected or corrected. Further, accurate information may not be available altogether due to a high speed of the processor; information may be skewed or missing.
Some systems include one or more dedicated functional units within the SOC that are dedicated to debugging the processor, sometimes referred to as a debug unit or module. However, these units affect the operation of the processor when obtaining information such as trace information. These units typically function at a lower speed than the processor, and thus affect processor operations when they access processor data. For example, when transmitting trace information off-chip, trace information may be generated at a rate that the debug module can process or transmit off-chip, and the processor must be slowed to avoid losing trace information. The debug module relies upon running debug code on the target processor itself, and this code is usually built into the system being debugged, referred to as the debugee. Thus, the presence of the debug code is intrusive in terms of memory layout, and instruction stream disruption.
Other debugging systems referred to as in-circuit emulators (ICEs) match on-chip hardware and are connected to it. Thus, on-chip connections are mapped onto the emulator and are accessible on the emulator which is designed specifically for the chip to be tested. However, emulators are prohibitively expensive for some applications because they are specially-developed hardware, and do not successfully match all on-chip speeds or communications. Thus, emulator systems are inadequate. Further, these systems generally transfer information over the system bus, and therefore necessarily impact processor performance. These ICEs generally use a proprietary communication interface that can only interface with external debug equipment from the same manufacturer.
Another technique for troubleshooting includes using a Logic State Analyzer (LSA) which is a device connected to pins of the integrated circuit that monitors the state of all off-chip communications. LSA devices are generally expensive devices, and do not allow access to pin information inside the chip. In sum, there are many systems which are inadequate for monitoring the internal states of a processor and for providing features such as real-time state and real-time trace in a non-intrusive manner.
Further, some debugging circuits make use of an interface referred in the art to as a JTAG (Joint Test Action Group) interface defined by IEEE 1149.1-1990 standard entitled Standard Test Access Port and Boundary-Scan Architecture. The specification was adopted as an IEEE standard in February 1990, and JTAG interfaces are commonly provided in integrated circuit systems. IEEE standard 1149.1 allows test instructions and data to be serially loaded into a device and enables the subsequent test results to be serially read out. JTAG interfaces are provided to allow designers to efficiently access internal parameters of integrated circuits to perform a boundary scan test on an integrated circuit (IC) device to detect faults in the IC. Boundary scan testing is well-known in the art of IC and ASIC development.
Every IEEE standard 1149.1-compatible device includes an interface having four additional pinsxe2x80x94two for control and one each for input and output serial test data. To be compatible, a component must have certain basic test features, but IEEE standard 1149.1 allows designers to add test features to meet their own unique requirements.
Some systems provide a method by which a JTAG interface associated with an integrated circuit may be reused to transfer debugging information. In one approach, a single JTAG instruction is used to place the JTAG port into a mode whereby JTAG pins are reused to form a link between the integrated circuit and another system. Signals on the JTAG pins in this mode are not conformant with the IEEE 1149.1 JTAG standard, nor do they obey any of the JTAG standard rules and thus cannot be connected to a standard JTAG device. In addition, the JTAG interface is a low-speed link, and is generally not capable of transferring information at a high rate of speed (in the MBit/s range of transmission and higher). Thus, an improved interface is needed for accessing an integrated circuit.
These and other drawbacks of conventional debug systems are overcome by providing an interface and protocol for communicating with an integrated circuit.
Further, a high-speed link is provided for obtaining information from an integrated circuit. Because the interface operates at a high rate of speed, real-time collection of trace information is possible. Further, the trace information transferred includes all of the information that an external system would use for debugging a processor. Also, the link may be memory-mapped such that an on-chip processor or other device associates with the integrated circuit may execute software located on the external system and on-chip devices may perform system bus transactions with a memory or storage device of the external system. In one aspect, the system includes an interface protocol that provides flow control between an integrated circuit and external system without requiring additional flow control pins.
According to another aspect of the invention, trace information communicated over the interface includes both address information and message information. In another aspect, the trace information includes timing information.
In another aspect of the invention, the link operates at a rate which is proportional to an operating rate of a processor system bus. In one aspect, the rate of the link changes as the rate of the system bus changes. Thus, debug information generated on-chip will not overwhelm the transmission capabilities link because the link speed is derived from the internal system bus rate.
In another aspect of the invention, an external system is capable of stopping, starting, and resetting the processor through the external link. In one embodiment, signals are provided for controlling the processor. In another embodiment, the external system is capable of writing to a register in a debug circuit to effect processor control.
In another aspect, the trace information may be compressed by the trace system. By compressing information, trace information is preserved for transmission over lower-bandwidth links and maximizes on-chip trace storage. For example, trace information may be compressed by compressing timestamp and address information. Further, trace information may be compressed by omitting duplicate types of information, such as one trace packet of a particular operation type. Also, information may be filtered by predefining criteria upon which trace information is generated. By filtering information and eliminating duplicate information on-chip, bandwidth requirements of links to external systems and on-chip storage requirements are reduced.
In another aspect, request information originating from an external device may also be compressed. In one embodiment, it is realized that the external system transmits only request messages, so that a message type field may be omitted. In another embodiment, transmission of information is minimized by transmitting, before a data message, status information indicating that a valid message is available to be transmitted.
In another aspect, a standard JTAG interface is used, and therefore, standard off-the-shelf JTAG components and JTAG commands may be implemented. Also, external systems such as debug adapter boards using JTAG components and the JTAG protocol may be reused for debugging different types of integrated circuits utilizing standard JTAG features.
According to another embodiment, both a JTAG interface and high-speed interface are available, and in one embodiment, both the interfaces implement an identical messaging protocol. Thus, because both interfaces utilize an identical messaging protocol, the amount of hardware in the integrated circuit may be reduced. Further, because the same messaging structures are used, the same functionality is provided for both interface types. Also, a mechanism may be provided wherein a link is selected automatically by the debug circuit or other device associated with integrated circuit 101, or is selectable by a user operating the external system.
According to another aspect of the invention, a message format is provided that minimizes the amount of information to be transferred over a JTAG interface. In particular, information regarding whether a message is available is transmitted before data information within a shift register.
These an other advantages are provided by a method for communicating between a debug circuit of an integrated circuit and an external system. The method comprises steps of sending a first request message; receiving a second request message, said second request message indicating that a receive processor may receive another request message; and sending a third request message. According to one embodiment, messages are transmitted over an output data path and are received over an input data path wherein the input and output paths operate independently from one another. According to another embodiment, the output data path is wider than the input data path.
The input data path may be, for example, 1 bit wide. According to one embodiment, the output data path is 4 bits wide.
According to another embodiment, the steps of sending request messages includes sending a start of message indication; and sending an end-of-message indication. According to another aspect, the request messages are system bus request messages.
According to one embodiment, contents of the request messages are identified and specify the response required to each request message. According to another embodiment, the system bus request messages originate from one or more devices coupled to a system bus associated with the integrated circuit.
According to another aspect, input data of an input message is provided in phase with an input clocking signal. According to one embodiment, output data of an output message is provided that is in phase with an output clocking signal. According to yet another embodiment, the third request message is located in a buffer, and is transmitted in response to receiving the second request message. According to another aspect, an output transmission clock used to clock output data is determined from an internal system bus clock. According to one embodiment, a programmable divider determines the output transmission clock frequency.
According to another embodiment, the programmable divider is programmed by a system external to the integrated circuit. According to another aspect, the output transmission clock is an integral frequency of the system bus clock. According to one embodiment, the system clock is dynamically changed to conserve power. According to another embodiment, the external system issues a command to transfer the processor from a standby state into an operating state. According to another aspect, the external system monitors a status indicator to determine if the processor is operating normally. According to one embodiment, the external system waits a predetermined amount of time to allow the processor to stabilize. According to another embodiment, the external system may perform one of either waiting a predetermined amount of time to allow the processor to stabilize; and monitoring a status indicator to determine if the processor is operating normally. According to another aspect of the invention, the external system delays sending of requests until the processor is operating normally.
According to one embodiment, an input message is compressed by omitting a type field.
According to another embodiment, an output message is a variable-length message determined by the contents of the message. According to another aspect, an output message is not dependent on debug adapter buffer status. According to one embodiment, the debug circuit indicates, in a bit of the output idle word, whether the receive buffer of the module is empty. According to another embodiment, output messages are one of trace messages and system bus transactions. According to another aspect, an idle word separates two output messages. According to one embodiment, the system bus transaction is a request to an address space of the external system.
According to another embodiment, a message type field of a trace message indicates that the trace message is at least one of, a trigger trace message type; and a background trace message type.
According to another aspect, the request to the address space of the external system is at least one of the group of reading from a memory address, storing to a memory address; and writing to a memory address and returning a previous value of the memory address.
According to another aspect, a method is provided for communicating between an integrated circuit and an off-chip device. The method comprises steps of transmitting a message off-chip at a transmission frequency proportional to an on-chip at a transmission frequency proportional to an on-chip system bus transmission frequency and automatically adjusting the transmission frequency in response to a change in bus transmission frequency.
According to another aspect of the inventions, an integrated circuit device is provided, the circuit comprising a first interface for communicating debugging information to an external device, a second interface for communicating debugging information to the external device, means for selecting at least one of first and second interfaces; and means for translating request from a system bus associated with the integrated circuit to at least one of the first and second interfaces.
According to another aspect, an integrated circuit is provided comprising an interface for communicating information to an external device and having an output buffer configured to store a plurality of data bits representing an output data message, the interface providing an indication to the external device that a data message is available to be transmitted to the external device.
According to another aspect of the invention, a data shift register is provided which is adapted to communicate message information. The shift register comprises a plurality of stored locations; and means for shifting a plurality of status bits, at least one of which indicating whether an output message stored in said storage locations is available to be transmitted, wherein said means shifts only the status bits out of the data shift register.
According to another aspect, an integrated circuit is provided comprising a communication circuit having a communication link coupling the integrated circuit and an external system, wherein the communication circuit is configured to transmit at least one of a group of messages including a request message including a system bus command for accessing a location in a memory of the external system; a response message including data produced in response to said system bus command; and a trace message.
Further features and advantages of the present invention as well as the structure and operation of various embodiments of the present invention are described in detail below with reference to the accompanying drawings. In the drawings, like reference numerals indicate like or functionally similar elements. Additionally, the left-most one or two digits of a reference numeral identifies the drawing in which the reference numeral first appears.